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Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 15

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

Section 3 : Function Description

The M6117D is designed to perform like Intel 386SX

system with deep green features. Aside from the 386SX

core, it contains (1) PS2/AT Keyboard Controller and

Mouse, (2) Real Time Clock to store system boot data, (3)

Programmable chip select, (4) Integrated System

Peripheral to serve the peripheral requests, (5) Power

Management Unit to reduce the chip’s power consumption

efficiently, (6) LS245 : TTL data buffer between ISA data

bus SD[7:0] and ROM data bus XD[7:0], (7) DRAM

Controller for four banks memory module supporting EDO

and Fast Page Mode with page interleave and up to 64M

bytes space, (8) IDE decoder function. The M6117D offers

the following blocks :

• Static 386SX Core

• Reset and Clock logic

• CPU Interface logic

• DRAM Controller

• Configuration Registers

• ISA Bus Interface logic

• Control logic

• Address Decode and Memory Mapping logic

• Data Buffer

• Address Buffer

• ISP Devices (82C37x2, 82C59x2, 82C54, 74LS612)

• Real Time Clock

• Real Time Clock interface

• PS2/AT Keyboard /Mouse Controller

• Keyboard and Speaker logic

• Parity Generation and Checking logic

• Power Management Unit

• WATCHDOG timer

• 16 bits GPIO

• IDE decoder interface

•

Programmable chip select

3.1 Static 386SX Core

The 386SX core is the same as M1386SX of Acer Labs.

Inc. and 100% object code compatible with the Intel 386SX

microprocessor. System manufacturers can provide 386

CPU based systems optimized for both cost and size.

Instruction pipelining and high bus bandwidth ensure short

average instruction execution times and high system

throughput. Furthermore, it can keep the state internally

from charge leakage while external clock to the core is

stopped without storing the data in registers. The power

consumption here is almost zero when clock stops. The

internal structure of this core is 32-bit data and address

bus with very low supply current, 116 mA in the conditions

of 5.0V, 20MHz, room temperature. Real mode as well as

Protected mode are available and can run MS-DOS,

MS-Windows, OS/2 and UNIX.

3.2 Reset and Clock logic

The switching power supply sends a PWG (power good

signal) to M6117D to generate system reset signals, like

RSTDRV, RESETL, and resets the chip to initial state.

Also the reset signal can be generated by internal

emulation RC reset and shutdown cycle.

There are two clock inputs: BCLK2 and OSC are 2X

system clock and 14.318MHz respectively, and three clock

outputs: BCLK1, ATCLK1 and CK7M which provide

frequency operation for the system board and devices

depending on 1X clock used. The BCLK1 is a half

frequency of BCLK2. The CK7M derived from the OSC

input (divided by 2) is available as the keyboard controller

clock when power is on. To increase system performance,

the M6117D supports variable AT clocks for faster ISA

add-on cards. When the CPU accesses the register

programmed special address range, the AT clock changes

to a faster speed. The non-programmed address regions

keep the normal speed. There are eight programmable

frequencies of the ATCLK1 which can change on fly by

different specific addresses and determined by D[2:0] of

local port 1EH in both high and normal speed. Please refer

to Section 4.2 index 1EH. This optional AT clock can

achieve a higher performance when a faster add-on card is

used.

3.3 Programmable Chip Select logic

For 386SX systems, M6117D generates GPCS0J,

GPCS1J to support the memory or I/O device. When

general purpose chip select is active, this indicated that an

15-bit channnel address and mask address are used to

specify a channel’s active address block. When the

processor access an address in memory or I/O, the upper

15-bit address are compared to the chip-select channel

address and OR’d with the channel mask. This means that

the chip select until compares the channel address and

ORs the channel mask to A25:A11 for memory address

and A15:A1 for I/O address.

3.4 DRAM Controller

The DRAM controller supports Fast Page Mode DRAM

and EDO DRAM.The DRAM controller is capable of

accessing up to 64 MBytes of local memory, and

supporting four banks page interleave of DRAM using

256K, 512K, 1M, 2M, 4M, 16M single sided SIMMs. Page

interleave mechanism is able to shorten the memory

read/write cycle and raise the data access speed between

host and RAM, and works on any two banks with the same

DRAM type. Each bank can be disabled through software,

please refer to 4.3 memory type configuration and 4.2

index 10H. When using EDO DRAMs, only page mode are

enabled. Programmable DRAM timing is provided for RAS

pre-charge time and RAS-to-CAS delay to achieve highest

performance and reliability, this part is described in 4.2

index 11H and 12H. And they also explain how to use the

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 111 112

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