386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.
DM&P M6117D : System on a chip
Page 34
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
4.6.9 Hard Disk Drive access
Hard disk drive operations will trigger SMI by programming
following control bits to ‘1’ = Index 57h :D[3], D[2] ;
5Ah:D[5], D[1] and 5Ch : D[5]. 12h will be shown on index
5Bh after HDD event.
4.6.10 Line Printer access
If indices 57h: D[4], D[3], 5Ah:D[5], D[2], and 5Ch:D[7] are
set to ‘1’, then it enables line printer access to activate SMI.
Index 5Bh will show 13h to manifest SMI cause from line
printer operation.
4.6.11 General purpose memory address access
If indices 6Ch, 6Dh, 6Eh, 6Fh were programmed in
advance and control bits 58h:D[0], 5Ah:D[3], 6Bh :D[1]
were set to ‘1’ (enable), then system will generate SMI
when memory read/write address matches the address
defined in indices 6Ch~6Fh, called GP0 event. For
example, If we write 10h to index 6Ch, 0Fh to index 6Dh,
00h to indices 6Eh and 6Fh, set index 58h: D[0], index
5Ah:D[3], index 6Bh: D[1] to high, then system will generate
SMI when memory read/write address is the one during
1MB~2MB. Index 5Bh will show 14h after GP0 event.
4.6.12 General Purpose I/O address access
Similar to CP0 access, SMI will occur when I/O read/write
address matches the address defined in index 70h, called
GP1 event. In addition to programming 70h and 6Bh, index
58h: D[1], index 5Ah :D[4] and index 6Bh:D[0] should be set
to ‘1’, thus GP1 event will be enabled and index 5Bh will
show 15h if any SMI occurs by GP1 event. Moreover, index
6Bh:D[7-4] offer three kinds of well defined I/O address
group to cause GP1 event.
4.6.13 Special instruction to emulate SMI
Instruction BRKPM, OP code = 0F1h, will emulate M6117D
entering HSM space as if SMI has occurred. This special
instruction is only for emulation or testing, no programming
is needed and of course index 5Bh will show nothing when
designer uses BRKPM instruction.
4.7 How to enter power saving mode
M6117D can stop internal clock to its CPU core that will
reduce almost 80% of its power consumption. Because our
chip belongs to pure CMOS process, it will keep the internal
states from leaking current when Vcc is still powered on
and clock has stopped. There is one control bit, called as
power clock stop (PCSTP), in internal control register to
determine if M6117D is going to enter power saving mode
or not. Here, we have a diagram to show the whole
operation on accessing power saving mode. Notice that
chip enters power saving mode by executing HALT
instruction, and leave by any interrupt or reset.
M6117D Power Saving Mode
Normal Bus Cycle
HALT cycle
Normal HALT mode
Power Saving mode
Coprocessor Cycle
or
Hold State
Halt instruction
PCSTP = 0
PCSTP = 1
NMI =1 or
INTR=1 or
Reset=1
NMI =1 or
INTR=1 or
Reset=1
HLDREQ=0
HLDREQ=1
HLDREQ=0
HLDREQ=1
Question : How to set PCSTP ? (Power Clock Stop)
Answer : MOV EAX, 00008000h
DB 0D6h, 0FAh, 03h, 02h
/* MOV PWRCR, EA0 */
(45 paginas)
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