Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC
M6117D : System on a chip
DM&P
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 5
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
All pins are 5V TTL compatible
Pin name Type Pin no. Description
Clock & Reset interface :
PWG I 113
Power Good. This indicates that the system power is enough to maintain
system integrity. It resets the system when the power is low.
BCLK2 I 39
CPU-bus Clock Input. This is the clock input source for the internal circuit.
The clock source should be the same as the CPU clock.
OSC14M I 117
14.318 MHz Oscillator. This frequency is 12 times the frequency used to
clock the 8254 timer counter.
ATCLK O 160
System Clock Output. This signal clocks the ISA bus.
RSTDRV O 162
Driver Reset. This output signal is driven active during system power up.
BCLK1 O 41
1X CPU-bus Clock. This is the clock divided by BCLK2.
RESETLJ O 120
Driver Reset LOW ACTIVE Output. This signal reset low active when
M6117D .
ISA Bus interface :
SD[15-0] I/O 13-9, 7-5,
138-145
ISA high and low byte slot data bus. These are the system data lines.
These signals read data and vectors into CPU during memory or I/O read
cycles or interrupt acknowledge cycles and outputs data from CPU during
memory or I/O write cycles.
SA[16-0] I/O 177-181
183-187
189-195
ISA slot address bus. These signals are high impedance during hold
acknowledge.
SA[17] I/O 176 ISA slot address bus for 62-pin slot.
SA[18] I/O 175 ISA slot address bus for 62-pin slot.
SA[19] I/O 174 ISA slot address bus for 62-pin slot.
LA[23-17] I/O 201-207
ISA latched address bus. These are input signal during ISA master cycle.
IO16J I 3 ISA 16-bit I/O device select indicator signal.
MEM16J I 4 ISA 16-bit memory device select indicator signal.
MASTERJ I 198
ISA master device active signal. ISA master access indicator signal.
MRDJ I/O 171
ISA memory read. This signal is an input during ISA master cycle.
MWTJ I/O 172
ISA memory write. This signal is an input during ISA master cycle.
AEN I/O 199
ISA I/O address enable. This active high output indicates that the system
address is enabled during the DMA refresh cycles.
IOCHRDY I 164
ISA system ready. This input signal is used to extend the ISA command
width for the CPU and DMA cycles.
BALE O 173
Bus address latch enable. BALE indicates the presence of a valid address
at I/O slots.
NOWSJ I 165
ISA zero wait state. This is the ISA device zero-wait state indicator signal.
This signal terminates the CPU ISA command immediately.
IOCHKJ I 196
ISA parity error. M6117D will generate NMI interrupt when this signal is
asserted.
BHEJ I/O 200
ISA byte high enable. In master cycle, it is an input polarity signal and is
driven by the master device.
IORJ I/O 166
ISA I/O read. This signal is an input during ISA master cycle.
IOWJ I/O 167
ISA I/O write. This signal is an input during ISA master cycle.
SMEMRJ O 168
ISA system memory read. This signal indicates that the memory read cycle
is for an address below 1M byte address.
SMEMWJ O 170
ISA system memory write. This signal indicates that the memory write
cycle is for an address below 1M byte address.
(45 paginas)
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