DMP Electronics eBOX-3350MX-AP Manual de usuario descargar pdf (Pagina 22)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 21

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

(e) Memory miss read RAS to CAS insert wait

When memory read miss. We can add 1T wait between the falling edges of both RASJ and CASJ, if D[2] of index 12h

is set to high.

BCLK2

RASJ

CASJ

WEJ

Insert wait 1T

COL addr ROW address COL address

(f) Memory fast write hit insert wait

When memory write hits. This factor is capable of activating CASJ at phase 1 or phase 2 of BCLK2. If D[0] of index 12h

is set to low, M6117D will activate CASJ at phase 2. In other words, the active CASJ will lag active RDYOJ by half

T-cycle. That is early ready timing. If D[0] of index 12h is set to high, chip will activate CASJ at phase 1. So that active

CASJ and RDY0J will be at the same phase.

(A) D[0] of index 12h is low

BCLK2

BCLK1

CASJ

RDYOJ

WEJ

COL 1

COL 2

COL 4COL 3

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 111 112

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DMP Electronics eBOX-3350MX-AP Manual de usuario Pagina 22