DMP Electronics eBOX-3350MX-AP Manual de usuario descargar pdf (Pagina 34)

Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC

M6117D : System on a chip

DM&P

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 33

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

timer will be reset when any key on keyboard is pressed for

keyboard is the most possible monitored peripheral device.

4.6.2 Interrupt request active

System will generate SMI as soon as any channel of 8259

 IRQ happened if we have already programmed index

5Ch and 5Dh. System

 definite instant SMI cause from it

has the most priority among all interrupts. Moreover, index

57h:D[3] and index 5Ah :D[5] should be set to ‘1’ to enable

IRQ trigger SMI. Index 5Bh will show 08h after this SMI

has occurred.

Index 5Ch Index 5Dh

D[7] IRQ7 selected D[7] IRQ15 selected

D[6] IRQ6 selected D[6] IRQ14 selected

D[5] IRQ5 selected D[5] IRQ13 selected

D[4] IRQ4 selected D[4] IRQ12 selected

D[3] IRQ3 selected D[3] IRQ11 selected

D[2] NMI selected D[2] IRQ10 selected

D[1] IRQ1 selected D[1] IRQ9 selected

D[0] IRQ0 selected D[0] IRQ8 selected

The M6117D has 49 configuration registers, these registers

reside at I/O port 23H (read/write), with index at output port

22H. Table 4-1 lists the internal registers summary.

Section 4.2 describes the bit function of internal registers.

Table 4-3 lists memory type configuration.

4.6.3 DMA channel request active

System will generate SMI as soon as any channel of 8237

 DRQ happened if we have already programmed index

5Eh, besides index 57h :D[7] and index 5Ah : D[6] should

be set to ‘1’ to enable DRQ trigger SMI. Here, index 5Bh

will show 09h after this SMI has occurred.

Index 5Eh

D[7] DRQ7 selected

D[6] DRQ6 selected

D[5] DRQ5 selected

D[4] DRQ4 selected

D[3] DRQ3 selected

D[2] DRQ2 selected

D[1] DRQ1 selected

D[0] DRQ0 selected

4.6.4 IN access

IN access will happen when monitoring IRQ12, IRQ4, IRQ3

and IRQ1 (always enable) are asserting. Index 66h:D[7-5]

is to define which IRQ channel is enabled as IN access,

notice that IRQ1 is always enabled. SMI occurs when

monitoring IN access is activating and then index 5Bh will

show 0Ah.

Index 66h

D[7] IN monitor IRQ3 select

D[6] IN monitor IRQ4 select

D[5] IN monitor IRQ12 select

4.6.5 External switch

There are two external trigger signals to generate SMI,

external SMI switch input (EXTSW2) and external suspend

switch input (EXTSW1), both of them have the same

function-trigger SMI. Index 58h :D[7-6] are the enable bits

to EXTSW2 and EXTSW1 respectively. Each input trigger

polarity can choose low-to-high active or high-to-low active

or both depending on index 67h: D[1-0] respectively.

These two input pins has internal debouncing circuit to

prevent the miss action. But you can bypass internal

debouncing circuit . Index 37H: D[5:4] are enable bits to

bypass EXTSW2 and EXTSW1 internal debouncing circuit

respectively. Index 5Bh will show 0Ch if SMI cause from

EXTSW1 and 10h if SMI cause from EXTSW2.

4.6.6 Real Time Clock alarm

System will generate SMI when IRQ8 assert, if RTC has

properly been programmed and the following control bits is

set to ‘1’ : index 57h :D[3], index 59h :D[6], index 5Ah :D[5]

and index 5Dh:D[0]. Index 5Bh will show 0Dh after this

event is asserted.

4.6.7 Software SMI

If index 56h :D[6] is set to ‘1’ and D[7] of the same register

is ‘1’, system will generate SMI called software SMI. Index

5Bh will show 0Fh after this event.

4.6.8 VGA access

If index 57h:D[1] and index 5Ah:D[0] are set to ‘1’, then

system will generate SMI when memory write address

matches 0A0000h~ 0B0000h with index 66h :D[0] is ‘1’, or

when I/O write address matches 3B0h~ 3BFh with index

66h :D[1] is ‘1’. Index 5Bh will show 11h after VGA access

event.

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