DMP Electronics eBOX-3350MX-AP Manual de usuario descargar pdf (Pagina 65)

386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.

DM&P M6117D : System on a chip

Page 64

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

Then the I/O port 04d0h and 04d1h can set the corresponding IRQ to be level trigger.

I/O port 04d0h - Interrupt controller 1

bit 7 - IRQ7

bit 6 - IRQ6

bit 1 - IRQ1

bit 0 - IRQ0

I/O port 04d1h - Interrupt controller 2

bit 7 - IRQ15

bit 6 - IRQ14

bit 1 - IRQ9

bit 0 - IRQ8

To enable IRQ10 to be level trigger, use

mov dx, 04d1h

in al, dx

IO_Delay

or al, 00000100 ; bit 2 - IRQ10

out dx, al

IO_Delay

5.6 PMU Programming Guide

5.6.1 Power Management Mode Selection

If any event happens, M6117D will check the setting of INDEX 55h and INDEX 38h to generate a signal.

1) SMI support :

mov ax, 05555h

call Read_From_Chip

and al, 11111100b ; SMI support

xchg ah, al

call Write_To_Chip

2) NMI support :

mov ax, 05555h

call Read_From_Chip

and al, 11111100b

or al, 00000001b ; NMI support

xchg ah, al

call Write_To_Chip

3) IRQ15 support:

mov ax, 05555h

call Read_From_Chip

and al, 11111100b

or al, 00000010b ; IRQ15 support

xchg ah, al

call Write_To_Chip

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 111 112

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DMP Electronics eBOX-3350MX-AP Manual de usuario Pagina 65

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