DMP Electronics eBOX-3350MX-AP Manual de usuario Pagina 19

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386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.
DM&P M6117D : System on a chip
Page 18
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
4.3 Memory Controller
4.3.1 How to enable/disable memory controller
Memory Controller will be enabled if D[7] of index 20h is
set to 1, or is disabled if reset D[7]. All original DRAM
cycles (local memory cycles) will turn to ISA bus cycles
when memory controller is disabled. Meanwhile, WEJ
and all RAS and CAS signals are driven high when
memory controller does not work. In other words, all
memory access will be treated as memory accessing on
ISA bus. Related timing waveforms, please refer to
Section 6.
4.3.2 How to set memory mode
Memory Controller supports Fast Page Mode and EDO
DRAMs. D[0] of index 37h is set to select which kind of
DRAM. The default is set to 0 to select Fast Page Mode
DRAM. When D[0] of index 37h is set to 1, DRAM is set to
EDO DRAM. EDO and Fast Page Mode DRAMs can not
mix, so only one type of DRAM can exist at the same time.
See Table below. There are 32 modes of memory type
configuration which supports up to six DRAM types
including 256K, 512K, 1M, 2M, 4M and 16M. Moreover,
various 30-pin or 72-pin single-sided SIMMs are available
on system design. We also offer a memory autosizing
method described by flow chart (Section 5.4 -A) to detect
memory mode on board as user reference.
Table 4-3 Memory Type Configuration
Mode BANK 0 BANK 1 BANK 2 BANK 3 Total Space PM(4:0)
0 256K*2 256K*2 1M Bytes 0 0 0 0 0
1 256K*2 256K*2 256K*2 256K*2 2M Bytes 0 0 0 0 1
2 256K*2 256K*2 1M *2 3M Bytes 0 0 0 1 0
3 256K*2 256K*2 1M *2 1M *2 5M Bytes 0 0 0 1 1
4 256K*2 256K*2 4M *2 9M Bytes 0 0 1 0 0
5 512K*2 1M Bytes 0 0 1 0 1
6 512K*2 512K*2
2M Bytes 0 0 1 1 0
7 512K*2 512K*2 1M *2 4M Bytes 0 0 1 1 1
8 512K*2 512K*2 1M *2 1M *2 6M Bytes 0 1 0 0 0
9 512K*2 512K*2 4M *2 10M Bytes 0 1 0 0 1
10 512K*2 512K*2 4M *2 4M *2 18M Bytes 0 1 0 1 0
11 512K*2 1M *2 3M Bytes 0 1 0 1 1
12 512K*2 1M *2 1M *2 5M Bytes 0 1 1 0 0
13 512K*2 4M *2 9M Bytes 0 1 1 0 1
14 1M *2 2M Bytes 0 1 1 1 0
15 1M *2 1M *2 4M Bytes 0 1 1 1 1
16 1M *2 1M *2 1M *2 6M Bytes 1 0 0 0 0
17 1M *2 1M *2 1M *2 1M *2 8M Bytes 1 0 0 0 1
18 1M *2 1M *2 4M *2 12M Bytes 1 0 0 1 0
19 1M *2 1M *2 4M *2 4M *2 20M Bytes 1 0 0 1 1
20 1M *2 4M *2 10M Bytes 1 0 1 0 0
21 1M *2 4M *2 4M *2
18M Bytes 1 0 1 0 1
22 1M *2 4M *2 4M *2 4M *2 26M Bytes 1 0 1 1 0
23 2M *2 4M Bytes 1 0 1 1 1
24 2M *2 2M *2 8M Bytes 1 1 0 0 0
25 2M *2 2M *2 4M *2 4M *2 24M Bytes 1 1 0 0 1
26 2M *2 4M *2 12M Bytes 1 1 0 1 0
27 4M *2 8M Bytes 1 1 0 1 1
28 4M *2 4M *2 16M Bytes 1 1 1 0 0
29 4M *2 4M *2 4M *2 24M Bytes 1 1 1 0 1
30 4M *2 4M *2 4M *2 4M *2 32M Bytes 1 1 1 1 0
31 16M *2 16M *2 64M Bytes 1 1 1 1 1
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